1. Field of the Invention
The present invention generally relates to input-output (I/O) electrostatic discharge (ESD) protection of integrated circuits. More specifically, the present invention is directed to an I/O ESD configuration with reduced parasitic loading on the I/O pad of an integrated circuit.
2. Background Art
Conventional integrated circuits typically require high quality I/O signal performance. The quality of an I/O signal is degraded by parasitic loading on the I/O pins, or pads, of an integrated circuit. The parasitic loading on the I/O pins is largely caused by the wire bonding structures and ESD protection structures that are included on each I/O port for manufacturability. The bonding structures and ESD protection structures introduce parasitic capacitances that can adversely affect I/O signal bandwidth. The I/O signal bandwidth supported by an I/O pin is reduced as the parasitic capacitance appearing at the I/O pin increases.
The parasitic capacitance of ESD protection structures is often non-linear. Therefore, the parasitic capacitance appearing at the I/O pin changes in a non-linear manner as the I/O signal changes. The result is a parasitic loading effect on the I/O pin that is I/O signal dependent, which causes I/O signal distortion or non-linearity. It is therefore desirable to minimize the parasitic capacitance of ESD protection structures to accommodate high quality I/O signal performance at the I/O port of the integrated circuit.
I/O ESD protection is often sacrificed to minimize the parasitic capacitance appearing at sensitive I/O pins. The ESD tolerance of an integrated circuit, however, is an important feature of integrated circuit manufacturing. Poor ESD tolerance can adversely affect product yield and reliability, particularly in high volume products or in products that may be exposed to handling. Therefore, it is essential to achieve an acceptable level of ESD protection, even in integrated circuits having high performance I/O ports.